`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:44:43 05/04/2013
// Design Name:   ALU
// Module Name:   T:/Lab3/tb_ALU.v
// Project Name:  Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ALU
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_ALU;

	// Inputs
	reg SUM;
	reg CMP;
	reg MUL;
	reg [N - 1:0] REGA;
	reg [N - 1:0] REGB;

	// Outputs
	wire [(2 * N) - 1:0] d_out;
	
	parameter N = 4;

	// Instantiate the Unit Under Test (UUT)
	ALU #(.N(4)) uut (
		.SUM(SUM), 
		.CMP(CMP), 
		.MUL(MUL), 
		.REGA(REGA), 
		.REGB(REGB), 
		.d_out(d_out)
	);

	initial begin
		// Initialize Inputs
		SUM = 0;
		CMP = 0;
		MUL = 0;
		REGA = 0;
		REGB = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		REGA <= 4'h5;
		REGB <= 4'h6;
		SUM <= 1;
		
		#100
		SUM <= 0;
		MUL <= 1;
		
		#100
		MUL <= 0;
		CMP <= 1;
	end
      
endmodule

